Copper post on chip is being used for high-performance flip chip packaging, particularly for finer pitch CPUs and high-end ASICs. Some of the issues with copper post on-chip are lower reliability with extreme low-k dielectrics and high cost. Tessera’s µPILR interconnect platform can be applied to flip-chip packaging and offers the advantages of copper post on-chip (fine pitch and good electromigration performance) while providing good reliability and lower cost.

By leveraging existing substrate fabrication and assembly processes and infrastructure, the µPILR platform offers a comprehensive foundation for attaching flip chip die to package via copper pillars on substrate, and provides a high aspect ratio interconnect with significant results:

• Scalability to < 100 µm pitch
  Allows higher I/O devices



• Higher Substrate and Assembly yields
  Elimination of solder on package pad



• Positive stand-off heights
  Provides predictable stand-off heights for high underfill yields even with collapsible lead-free solder bumps



• High reliability
  Lower stresses on low-K dielectrics than Cu pillar on-chip



• Greater electromigration resistance
  Chip pad size reduction not required for reduced pitch