|
| |
| |
| Package Substrate |
|
| μPILR™ Package-on-Package (PoP) Interconnect Solution |
| |
| The ever increasing demand for mobile electronic products with more features and greater functionality poses an ongoing challenge to manufacturers to meet performance, form factor and cost objectives. Higher device functionality demanded for mobile computing, game consoles and handheld devices drives the need for more powerful combinations of memory, logic and analog semiconductors to be packaged in a smaller total space, while still maintaining performance, reliability and configuration flexibility. |
| |
μPILR PoP Substrate - Top and Bottom Packages |
| |
| Innovative Logic and Memory Solutions for Next-Generation Products |
| |
|
Tessera’s µPILR™ Package-on-Package (PoP) interconnect solution enables chip manufacturers to overcome these challenges by providing a 3D stacking solution that delivers greater functionality, a reduced package footprint and superior reliability for handheld mobile products.
Tessera’s advanced µPILR PoP interconnect solution differs from conventional ball grid array (BGA) semiconductor packaging by replacing solder balls with an array of short, highly uniform copper contacts that improve the form factor, performance and reliability of the package. The post-like shape of these copper contacts enables a contact pitch tighter than traditional BGA devices. |
|
| Features and Benefits of µPILR PoP Substrate include: |
|
- High routing density
Allows smaller footprint and lower costs
- Lowest available package profile for single packages and PoP
Essential in hand held devices
- High surface mount yields at very fine interconnect pitch
High manufacturing yield and less rework
- Wide range of stand-off heights for package-on-packages stacking
Enables small footprint with stacked devices in lower PoP package
- Superior drop test and thermal cycling performance
High reliability with no underfill required
- Use of standard material and processes for assembly
No up-front infrastructure investment
- Improved test contact from nickel/gold plated pins
Low false failures and infrequent socket maintenance |
| |
μPILR PoP Cross Section |
| |
| DRAM Stacking |
| |
|
Stacked DRAM memory solutions have become critical in improving server management, efficiency and costs. The low profile and short interconnect of μPILR technology, along with the associated thermal performance, makes it an ideal package stacking choice for certain current and next-generation DRAMs used in servers and data centers. |
| |
| Fine Pitch and High I/O Package Stacking |
| |
|
The μPILR PoP interconnect solution enables the integration of functionality and continuing miniaturization of electronic devices. Validated by several electronic manufacturers, semiconductor assemblers and substrate suppliers, the μPILR PoP solution is an ideal platform for applications requiring fine pitch and high I/O package stacking. |
| |
 Download the μPILR PoP Flyer |
| Read the White Paper: Reliability of μPILR™ Packages under Shock Loading |
| Read the White Paper: Micro Copper Contacts Replace BGA, Improve Reliability |
| Read the White Paper: Package Reliability Using μPILR in Stacking and Flip Chip |
| Read the Article: Package-on-Package is Killer App for Handsets | |
| |
|
|
|
|
|