Tessera provides innovative technologies that are transforming next-generation wireless, consumer and computing products.

Home Page About Tessera Technologies Applications Careers Contact Tessera
 
Tessera Technologies, Inc.,Technologies, packaging and interconnect solutions, semiconductor miniaturization, imaging and optics solutions
 
 
Flip Chip Technology
μPILRTM Interconnect Platform
 

Flip chip packaging has long been the highest performance packaging solution available in the industry. It is the preferred solution for CPUs/MPUs, high-end ASICs and other high-IO and high speed devices.

Tessera pioneered electronics miniaturization with its foundational Tessera Compliant Chip® (TCC) chip scale packaging (CSP) technology is applying its extensive semiconductor packaging expertise to deliver solutions that overcome challenges in reducing pitch, increasing substrate yield, controlling electromigration, reducing stress on extreme low-k dielectrics, and other limitations of many approaches on current flip chip technology roadmaps.

 
Tessera Technologies, μPILR Flip-Chip Substrate
μPILR Flip-Chip Substrate 
 
 
 

Copper post on chip is being used for high-performance flip chip packaging, particularly for finer pitch CPUs and high-end ASICs. Some of the issues with copper post on-chip are lower reliability with extreme low-k dielectrics and high cost. Tessera’s µPILR interconnect platform can be applied to flip-chip packaging and offers the advantages of copper post on-chip (fine pitch and good electromigration performance) while providing good reliability and lower cost.

By leveraging existing substrate fabrication and assembly processes and infrastructure, the µPILR platform offers a comprehensive foundation for attaching flip chip die to package via copper pillars on substrate, and provides a high aspect ratio interconnect with significant results:

  • Scalability to < 100 µm pitch
    Allows higher I/O devices

  • Higher Substrate and Assembly yields
    Elimination of solder on package pad

  • Positive stand-off heights
    Provides predictable stand-off heights for high underfill yields even with collapsible lead-free solder bumps

  • High reliability
    Lower stresses on low-K dielectrics than Cu pillar on-chip

  • Greater electromigration resistance
    Chip pad size reduction not required for reduced pitch
 
Tessera's extensive research and development centers in San Jose, California and Yokohama, Japan are extending the µPILR interconnect platform to provide innovative advanced, fine pitch solutions for flip chip packaging. For further information about flip chip or other µPILR technologies, contact us today.
 
 
footer
 © Copyright 2014 Tessera, Inc. All Rights Reserved.  Legal Info  |  Privacy Policy                                                        Home  |  about tessera  |  technologies  |  applications  |  careers  |  contact us  |  site map