Overview
Wafer Level Packaging (WLP) is a chip-scale packaging (CSP) technology where all the steps of IC packaging are performed at the wafer level. This packaging approach is currently being utilized for small die with relatively low I/O, such as linear, analog, and integrated passive devices. In the future, wafer level packaging will likely be applied to larger die and higher I/O devices, such as memory, baseband processors, and ASICs.
Since the mid-90s, Tessera has created an extensive intellectual property portfolio in the area of WLP and, in fact, continues to innovate wafer level solutions to address the ever-increasing demands for miniaturization, lower cost, increased functionality and higher reliability.
Tessera's WLP technology typically utilizes a compliant layer to minimize reliability issues due to the thermal expansion mismatch between the semiconductor device, usually silicon, and the printed circuit board (PCB) to which the package is mounted, while at the same time maintaining high performance and low cost. This approach effectively enables WLP to be applied to larger, higher I/O devices today.
Cost, size, test and burn-in are major driving forces in the packaging industry. Wafer level packages offer certain advantages over traditional packaging technology that directly impact these trends.For example, package assembly, burn-in and final test at the wafer level can lead to substantial cost savings due to WLP's massively parallel processing and testing potential. In addition, handling and shipping logistics can be streamlined and reductions in cycle time realized if wafer level packaging is added to the backend of a wafer fab.
If you are interested in learning more, please contact us at info@tessera.com. |
