SHELLCASE® RT Tessera’s SHELLCASE® RT Wafer-Level Chip-Scale Packaging (WLCSP) technology, is now available for packaging 300mmm (12”) wafers. The SHELLCASE solution is a high-yield, highly reliable manufacturing solution for image sensors used in next-generation mobile devices including mobile phones and PDAs. The technology enables very low profile camera modules, providing OEMs with greater design flexibility and an innovative tool in the development of thinner mobile devices.
SHELLCASE RT is based on SHELLCASE’s core wafer
level technology family, utilizing an innovative polymeric encapsulated
glass-silicon structure to enable
image-sensing capabilities through
the actual packaging structure.
The result is a true die-sized package
with X/Y dimensions identical to the
original chip size, and a total package
height which is almost half of the
original silicon thickness.
SHELLCASE RT is offered in both
cavity and non-cavity formats;
In the cavity format, there is a cavity
space between the image area and
the cover glass, allowing for the use
of micro-lenses, whereas in the non-
cavity format, the glass is applied
directly on the image sensor.
Benefits
Economies of scale enabled by
wafer- level packaging
High yields largely irrespective of pixel size of resolution:
Packaged device approximately
half of the original silicon thickness
Optical properties are characterized by a glass cover with a transmittance
of 91.2% in the 350-900nm range
Extremely accurate die rotation control during assembly (max. < ± 0.010)
Package height <250 μm
Precise die tilt control of <0.5mil during assembly
Flexible cavity height
Termination type: BGA or LGA
Applications
Camera phones
Digital cameras
Automotive electronics
Fax machines and digital scanners
Machine vision
CD/DVD portable players
Reliability
SHELLCASE RT offers superior
reliability and corrosion resistance as
a result of its optimized design,
materials and processes.
Moisture
Sensitivity
JEDEC Level 1
Temperature Humidity
85 ºC / 85%RH,
2000 hrs
High
Temperature
Storage
150 ºC, 2000 hrs
Thermal Cycling
-40 ºC /+ 125 ºC, 2000 cycles
Process Highlights
Image area encapsulated by glass
from the initial stage
Very precise wafer-level bonding +/-15µm
For cavity format, tight Z-focal
tolerance from image area to
bottom of cover glass is possible
Available in both lead and lead-free
bump formats
Most Innovative Product
Tessera Inc., SHELLCASE® RT wafer-level chip-scale packaging technology
SHELLCASE® RT, a wafer-level chip-scale packaging (WLCSP) technology, targets OEMs and camera-module manufacturers building lower profile camera modules for camera phones, PDAs, laptops, and automotive-based electronics. It leverages existing assembly processes and infrastructure and supports lead-free production. The technology incorporates polymeric-encapsulated glass-silicon structures, wherein the wafer is encapsulated with a glass cover at the initial stage of processing; electrical contacts are routed to the wafer backside where solder bumps are formed. The wafer is singulated into individually packaged dice in both cavity and non-cavity formats. At approximately 0.5mm thickness, the platform accommodates scribe lines down to 100-micron, smaller bond pads, and pitches down to 180-micron. It achieves 2000 cycles and thermal temperature ranges of -40-125iC. Tessera Inc., San Jose, CA, United States; ph 408/894-0700, www.tessera.com.
SHELLCASE® RT
