• Increased memory density within the same footprint
• Flexible design for a single, two and four layer DRAM solution
• Low profile enabled by leveraging solder ball height
• Short trace lengths and wire-bond interconnections ensure high electrical and thermal performance
• Exposed back surface of the die provides good thermal management
• Test before stack option results in near 100% final package yield
• No board-level underfill is required, providing the option for rework
• µBGA^® technology provides design flexibility to utilize wire or lead-bond interconnect technology, perimeter and/or center-bond orientation, polyimide or low cost laminate-based substrates
• Standard CSP/BGA assembly, materials, and SMT processes
• Lead-free compatible

2-Die µZ^TM Ball Stack comparison with Standard TSOP